A knock against software defined hardware using “white-box” CPUs is its performance compared to purpose-built hardware that incorporates ASICs or FPGAs (Field Programmable Gate Arrays). ASICs (Application Specific Integrated Circuits) perform, but cannot adapt as needed. FPGAs provide flexibility, but programming in VHDL isn’t a skillset of the typical IT network administrator. Enter Netcope Technologies and their demonstration of their P4 to VHDL compiler and Netcope FPGA (PCI Express) Board (NFB) that plugs into commodity PC hardware.

In the above video, Lukas Richter, Business Development Manager for Netcope Technologies, a.s., demonstrates a configuration of two NFBs, whereby one NFB is configured as a 100 Gb/s traffic generator/receiver, which feeds a second NFB that is adding a VLAN tag to a specific IP address. Other functions that Netcope has created using this technology include 100 Gb/s deep packet inspection, specialized routers for high-speed, low-latency financial trading and network monitoring.

What gives the Netcope products the ability to easily shape-shift from one network function to another is the aforementioned P4 to VHDL compiler, which takes the burgeoning P4 language of network administrators and converts it to commands (VHDL) understood by FPGAs.

As background, P4 is an open source, high-level programming language that has grown to over 60 members, including AT&T, Intel and Google. First suggested in a paper published in July 2014, the authors’ goals were:

“(1) Reconfigurability in the field: Programmers should be able to change the way switches process packets once they are deployed. (2) Protocol independence: Switches should not be tied to any specific network protocols. (3) Target independence: Programmers should be able to describe packet processing functionality independently of the specifics of the underlying hardware.”

As explained in this post, like OpenFlow, it opens up the forwarding plane, but the distinction is that P4 addresses the need to program the data plane. Instead of the hardware limiting what can be done, P4 provides a way to tell the hardware what to do and how it should process packets.